Limited by array leakage and read stability, CMOS SRAM cell device threshold voltages (VT) have scaled less aggressively than logic requiring a separate, higher supply voltage (VDD-CELL) to enable higher static noise margin (SNM) and read current (IREAD), and lower read current variability, in the presence of increasingly severe, random VT fluctuations in small geometry SRAM cell transistors. However, a second array of power supply translates into more input output (I/O) requirements and fewer metal wiring tracks for other chip functions such as power, global signal and clock distribution—all of which directly impact cost. Secondly, higher/dual cell power supplies result in (i) more leakage due to all components from unaccessed Subarrays of large L2 caches during active mode and (ii) more switching power, adversely impacting battery lifetime for portable applications as well as the cost of packaging for high performance desktop and server products.
New circuit techniques were reported in a co-pending application YOR9200300292US1 by some of the present authors that enable a single VDD SRAM to operate at logic compatible voltages with a cell read current and cell static noise margin typically seen with higher/dual VDD SRAMs. The schematic circuit implementations are shown in FIGS. 1a, 1b and 2. FIG. 3 shows the physical implementation of the SRAM cell interconnects schematically where the array of word lines (WL) and the associated power lines (PL) are shown. Implemented in a 65 nm CMOS SOI process with no alterations to the CMOS processes and materials or to a conventional, single VT SRAM cell, the voltage across power rails of the selected SRAM cells self-biases to permit a higher-than-VDD voltage during word line (WL) active periods and a lower than 2VT voltage at all other times. Based on circuit simulations data, FIG. 4, this “bootstrapping” has been shown to increase the supply voltage by about 17% under this circuit implementation. Bootstrapping the cell row power supply and regulating the cell Subarray virtual ground voltage enables the above ‘Transregional’ SRAM operation resulting in near-subthreshold data storage and superthreshold access, lowering total leakage by over 10× and improving IREAD and SNM by 7% and 18% respectively with a total area overhead of less than 13%.
It is therefore clear that ‘Transregional’ SRAM operation enables logic VDD compatibility, lower leakage, and higher cell read stability without degradation of performance. The benefits of this bootstrapping effect can be significantly enhanced over those shown in prior art by enabling a stronger capacitive coupling between the WL that selects a row of SRAM cells and the power line (PL) pair that supply power to that row. Incorporation of a higher k dielectric material between the WL and PL lines in an SRAM subarray, to enable a stronger capacitive coupling between WL and PL is a way to achieve this end. However, using a higher k dielectric at other the regions of the chip (areas of logic and interconnects) is detrimental to chip performance as increased capacitance in these regions translates to increased RC delay and hence slower interconnect speeds. In this invention, we teach a structure that enables higher capacitive coupling in the SRAM cell areas and lower capacitance elsewhere so as to overcome this problem. Several methods to fabricate such a structure are also taught.
It is therefore an object of this invention to describe a chip interconnect structure that will enable a hybrid system of inter-metal dielectrics (IMD): a high k or ultra-high k dielectric in the inter-metal gaps between the WL and PL features, FIG. 5, while providing low k or ultra low k dielectric separating the interconnect lines elsewhere. For the purpose of convenience in the descriptions below we arbitrarily define high k as 7<k<4 and ultra high k as k>7 and low k as 4<k<2.0 and ultra low k as k<2. It is further the object of this invention to achieve the optimum benefits in the SRAM performance metrics as outlined above while maintaining the mechanical robustness of the chip and the low effective interconnect capacitance to minimize interconnect delay elsewhere on the chip. It is further an object of this invention to describe methods to fabricate the above described hybrid interconnect structure.
These and other aspects of our invention are described below in detail along with the following set of illustrative figures.